Jone F Chen
National Cheng Kung University, Taiwan
Title: Effect of dimension on characteristics and reliability of high voltage MOS transistors
Biography
Biography: Jone F Chen
Abstract
High voltage metal-oxide-semiconductor (MOS) transistors have been widely used in smart power management applications because of their compatibility with standard complementary metal-oxide-semiconductor (CMOS) process. Because high voltage MOS transistors are operated under high voltage, the off-state breakdown voltage and on-state drain current are two key device parameters. In addition, hot-carrier induced device degradation is an important reliability concern. One key factor to affect the off-state breakdown voltage, on-state drain current, and hot-carrier induced device degradation is the dimension of the device. In this paper, the effect of device dimension on device’s characteristics and hot-carrier reliability in our high voltage MOS transistors is investigated. Figure 1 shows the schematic cross section of the Si-based n-type high voltage MOS Transistors examined in this paper, where three important layout parameters: Lgs, Lg, and Lgd are depicted. The device with typical dimension (device A) and three more dimensions (devices B, C, and D with individually shortening Lgs, Lg, and Lgd by 0.1 mm) as seen in Figure 1 are examined. The effect of varying Lgs, Lg, or Lgd on off-state breakdown voltage, on-state drain current, and hot-carrier induced device degradation are examined. It was found that shortening Lgs, Lg, or Lgd enhances on-state drain current but degrades hot-carrier induced device degradation. Both experimental data and technology computer-aided-design (TCAD) simulation results are analyzed to explain the underlying physical mechanisms. Our findings reveal that care should be taken in determining the device dimension because a trade-off between on-state drain current and hot- carrier induced device degradation is observed.
Recent Publications
1.Moens P, Mertens J, Bauwens F, Joris P, De Ceuninck W, Tack M (2007) A comprehensive model for hot carrier degradation in LDMOS transistors. Proc. IRPS: 492-497.
2.Enichlmair H, Park JM, Carniello S, Loeffler B, Minixhofer R, Levy M (2009) Hot carrier stress degradation modes in p-type high voltage LDMOS transistors. Proc. IRPS: 426-431.
3.Poli S, Reggiani S, Baccarani G, Gnani E, Gnudi A, Denison M, Pendharkar S, Wise R (2011) Full understanding of hot-carrier- induced degradation in STI-based LDMOS transistors in the impact-ionization operating regime. Proc. ISPSD: 152-155.
4.Chou HL, Huang CF, Gong J (2013) Dimension dependence of unusual HCI-induced degradation on N-channel high-voltage DEMOSFET. IEEE Trans. Elec. Dev. 60: 1723-1729.